The present invention relates to a semiconductor memory device; and, more particularly, of a delay locked loop having the ability to drastically eliminate noise.
In general, a delay locked loop (DLL) circuit reduces a skew between a clock signal and data or between an external clock and an internal clock, which is used in synchronizing an internal clock of a synchronous memory to an external clock without incurring any error. Specifically, a timing delay is incurred when an external clock is used internally to a system, and the delay locked loop controls the timing delay to synchronize the internal clock to the external clock.
FIG. 1 is a schematic block diagram of a conventional delay locked loop.
A clock signal Clock_1 is input to a controllable delay modification unit 100 which delays the input signal by a certain time period and produces a time-delayed signal Delayed_clock to a comparator 110. The comparator 110 compares the time-delayed signal Delayed clock and a reference signal Clock_reference, and determines if the time delay should be increased (added) or decreased (subtracted), to produce one of an addition signal Add_delay or a subtraction signal Subtract_delay. The addition signal Add_delay or the subtraction signal Subtract-delay output from the comparator 110 is fed back to the controllable delay modification unit 100. Based on the addition signal or the subtraction signal, the controllable delay modification unit 100 modifies the time delay until the reference signal Clock_reference and the time-delayed signal Delayed_clock are synchronous in phase.
As mentioned above, the prior art is designed so that the comparator 110 determines if the time delay fed thereto from the controllable delay modification unit 100 should be increased or decreased and returns the result to the controllable delay modification unit 100 to thereby allow the time delay to be adjusted.
However, the prior art has a drawback that it is very sensitive to a power supply noise, random noise, radiation noise or other irregular noise. That is, the erroneous determination of the comparator 110 due to such noises causes an output signal to be fed back to the controllable delay modification unit 100 to be erroneous. As a result, the controllable delay modification unit 100 controls the time delay based on the erroneous signal, resulting in an unintended problem.
It is, therefore, a primary object of the present invention to provide a delay locked loop having the ability to reduce or eliminate a power supply noise, a random noise or other irregular noise.
In accordance with a preferred embodiment of the present invention, there is provided a delay locked loop for use on a semiconductor memory device, which comprises: a controllable delay modification unit for delaying a clock signal fed thereto to produce a time-delayed signal; a comparator for comparing the time-delayed signal from the modification unit and a reference signal, and determining an addition or subtraction of the time delay according to the compared result to produce a corresponding output signal; and a delay control unit for counting occurrences of the corresponding output signal and producing a signal for controlling the addition or the subtraction of the time delay to the controllable delay modification unit, if the counted value is larger than a predetermined value.